This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-060480, filed Mar. 6, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a power semiconductor element including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in a power inverter and a method of fabricating the same, particularly, to an element structure capable of improving the short circuit withstand capability and a method of fabricating the same. The present invention is applied to, for example, an IGBT (Insulated Gate Bipolar Transistor) a power MOSFET, a MCT (MOS Controlled Thyristor), and an IEGT (Injection Enhanced Gate Transistor).
In recent years, the power source apparatus used in the field of the power electronics is required to be miniaturized and to exhibit a high performance. Therefore, in the power semiconductor element (switching element), vigorous efforts are being made in an attempt to improve the performance of the power source apparatus in respect of the improvements in the breakdown voltage, in the adaptability for the large current, in the reduction of the loss, in the withstand capability to the breakdown, and in the operating speed. Particularly, a power IBGT excellent in the breakdown voltage and in the adaptability for the large current and capable of obtaining an ON-voltage lower than that of the power MOSFET is widely used as a power semiconductor element having a breakdown voltage not lower than about 300 V.
The power IGBT is an element that is driven by a MOS gate. Widely known to the art are two kinds of the power IGBT, i.e., a power IGBT of a planar structure, in which a MOS gate is formed in the shape of a flat plate, and a power IGBT of a trench structure, in which the MOS gate is buried inside a trench.
The trench IGBT has a trench-gate structure in which a large number of trench IGBT cells each including a channel region formed of the trench side wall are arranged on a semiconductor substrate. In general, the trench IGBT is said to be advantageous over the planar IGBT in that the trench IGBT permits easily improving the performance (or permits decreasing the loss) by the reduction of the channel resistance. The construction of the trench IGBT will now be described with reference to FIG. 1A, which is a cross sectional view schematically showing the construction of a conventional trench IGBT.
As shown in FIG. 1A, an n+-type buffer layer 11, an n-type base layer 12, and a p-type base layer 13 are formed in the order mentioned on a p+-type collector layer 10. Also, an n+-type emitter layer 14 is in a part of the surface region of the p-type base layer 13. Also formed is a trench 15 extending downward from the surface of the emitter layer 14 to reach the n-type base layer 12 through the emitter layer 14 and the p-type base layer 13. A gate electrode 17 (trench-gate electrode), which is covered with a gate insulating film 16, is buried in the trench 15. The trench-gate electrode 17 is withdrawn to reach, for example, a pad (not shown) for the gate electrode for contact with the outside.
An emitter electrode 18 is formed to cover the emitter layer 14 and the p-type base layer 13. The emitter layer 14 and the p-type base layer 13 are electrically short-circuited by the emitter electrode 18. Also, an insulating film 19 is formed on the trench-gate electrode 17. The trench-gate electrode 17 and the emitter electrode 18, are electrically isolated from each other by the insulating film 19. Also, a collector electrode 20 is formed on the back surface of the collector region 10.
A MOSFET is formed of the nxe2x88x92-type base layer 12, the p-type base layer 13, the emitter layer 14, the gate insulating film 16 and the trench-gate electrode 17. It should be noted that electrons are injected from the emitter layer 14 into the nxe2x88x92-type base layer 12 through a channel region CH formed in that region of the p-type base layer 13 which is in contact with the trench 15.
FIG. 1B is a graph relating to an impurity concentration profile along the line X1-X2 shown in FIG. 1A and shows the impurity concentration distribution in the active area including the channel region CH. As shown in the drawing, the profile includes the n-type impurity concentration distribution 30 in the emitter layer 14, the p-type impurity concentration distribution 31 in the p-type base layer 13, and the n-type impurity concentration distribution 32 in the nxe2x88x92-type base layer 12. The p-type impurity concentration in the p-type base layer 13 is increased to reach the highest concentration Cp0 in the position close to the junction between the emitter layer 14 and the p-type base layer 13, and the p-type impurity concentration is gradually lowered toward the nxe2x88x92-type base layer 12.
The fabricating process of the trench IGBT shown in FIG. 1A will now be described briefly. In the first step, the p-type base layer 13 is formed by diffusion in a surface region of the nxe2x88x92-type base layer 12 formed on the collector region 10 with an n-type buffer layer 11 formed therebetween. Then, a large number of n-type emitter layers 14 having a stripe pattern when viewed from above are formed in a surface region of the p-type base layer 13. As a result, the exposed portion of the p-type base layer 13 is allowed to have a large number of stripe pattern as viewed from above.
Then, the trench 15 having a stripe pattern as viewed from above are formed in each of the emitter layers 14 in a manner to extend to reach the n-type base layer 12. In other words, the trench 15 is formed to extend through the emitter layer 14 and the p-type base layer 13. After formation of the trench 15, the gate insulating film 16 such as a SiO2 film is formed to cover the inner wall of the trench 15 and the upper surfaces of the emitter layer 14 and the p-type base layer 13.
In the next step, a polycrystalline silicon (polysilicon) film 17 containing P (phosphorus) is formed by a CVD (Chemical Vapor Deposition) method within the trench 15 and on the surfaces of the emitter layer 14 and the p-type base layer 13. The polysilicon film 17 is for formation of the trench-gate electrode.
Then, the polysilicon film 17 is patterned on the basis of the trench gate lead pattern so as to form a pad (not shown) for contact of the gate electrode. Also, the upper surface of the polysilicon film 17 within the trench 15 is etched back so as to permit the upper surface of the gate electrode 17 to be flush with the upper surfaces of the emitter layer 14 and the p-type base layer 13.
Then, an insulating film 19 is deposited on the upper surfaces of the trench 15, the emitter layer 14 and the p-type base layer 13, followed by forming a large contact hole for the lead of the gate electrode in the insulating film 19 formed on the pad for contact of the gate electrode. Also formed is a contact hole for the lead of the emitter-base in a manner to extend through the insulating film 19 around the opening of the trench 15 and through the gate insulating film 16 positioned below the insulating film 19.
Further, a metal wiring layer such as an aluminum wiring layer is formed by a sputtering method within the contact holes and on the insulating film 19 for the lead of the gate electrode and for the lead of the emitter-base, followed by patterning the metal wiring layer as desired so as to form an emitter electrode 18 and a gate electrode wiring (not shown). Still further, a collector electrode 20 is formed on the back surface of the collector layer 10, thereby forming the trench IGBT.
The operation of the trench IGBT shown in FIG. 1A will now be described.
When the IGBT is turned on, a collector voltage VCE is applied between the collector electrode 20 and the emitter electrode 18. At the same time, a positive gate voltage VGE is applied between the trench-gate electrode 17 and the emitter electrode 18. As a result, an inverted layer (n-type channel) whose conductivity type is inverted from the p-type to the n-type is formed in the channel region CH of the p-type base layer 13. Electrons are injected from the emitter electrode 18 into the nxe2x88x92-type base layer 12 through the inverted layer, and the injected electrons are allowed to migrate through the n+-type buffer layer 11 to reach the p+-type collector layer 10. It should be noted that, since a forward bias is applied between the p+-type collector layer 10 and the nxe2x88x92-type base layer 12, holes are injected from the p+-type collector layer 10 into the n+-type base layer 12. Since both electrons and holes are injected into the nxe2x88x92-type base layer 12, the conductivity is modulated in the region of the nxe2x88x92-type base layer 12 so as to markedly decrease the resistance of the nxe2x88x92-type base layer 12. As a result, the IGBT is turned on.
When the IGBT is turned off, a negative voltage relative to the emitter electrode 18 is applied to the trench-gate electrode 17. As a result, the inverted layer is caused to disappear, with the result that the electron injection from the emitter layer 14 into the nxe2x88x92-type base layer 12 is stopped. On the other hand, the holes accumulated in the nxe2x88x92-type base layer 12 are partly discharged through the p-type base layer 13 into the emitter electrode 18. The remaining holes are recombined with the electrons so as to be caused to disappear, thereby turning off the IGBT.
Where the load is short-circuited in the IGBT having the construction and operation as described above, the power source voltage is applied to the collector electrode 20 when the IGBT is under the conductive state. In this case, a short circuit peak current Icp flows through the IGBT, with the result that the IGBT is broken down a certain time tsc later. The time between the short-circuiting of the load and the breakdown of the IGBT is called herein the short circuit withstand capability tsc. It has been confirmed that the short circuit withstand capability tsc is diminished with increase in the short circuit peak current Icp of the IGBT because of the thermal breakdown caused by the short circuit peak current.
The conventional trench IGBT described above has the advantage that it is possible to increase the channel density so as to decrease the on-voltage. However, if the channel density is increased, the current flow is facilitated, with the result that the short circuit peak current Icp is increased and the short circuit withstand capability tsc is diminished. In other words, the on-voltage and the short circuit withstand capability have a trade-off relationship.
Incidentally, various constructions in addition to the construction shown in FIG. 1A are proposed in respect of the conventional IGBT. For example, proposed is the construction that, where the distance between the adjacent trench-gate electrodes 17 (cell pitch) is relatively large and the width of the contact opening is large to some extent compared with the processing accuracy in the construction shown in FIG. 1A, the short circuit between the emitter layer 14 and the base layer 13 is achieved by the emitter electrode 18 in the entire surface in a direction parallel to the trench 15.
On the other hand, if the cell pitch is diminished, the width of the contact opening is diminished, with the result that it is difficult to achieve the short circuit between the emitter layer 14 and the base layer 13 by the emitter electrode 18 in the entire surface in a direction parallel to the trench.
In order to solve the problem described above, it is proposed to form the emitter layer 14 of the trench IGBT to have a ladder-like pattern as viewed from above. In other words, it is proposed to form the trench IGBT such that rectangular exposed portions of the base layer 13 are dotted.
It is also proposed to form the trench IGBT such that the emitter layer 14 as a whole has a mesh-like (or a lattice-like) pattern or a mesh-like (or zigzag patterned lattice-like) pattern having an offset as viewed from above. In other words, it is proposed to form the trench IGBT such that the band-like emitter layer 14 and the band-like exposed portions of the base layer 13 are alternately present along the trench 15.
Further proposed is a trench contact structure in which a trench for the emitter contact is formed in that portion of the base layer 13 which is positioned between the adjacent emitter layers 14, and the emitter electrode 18 is formed in contact with the side surface of the emitter layer 14 and with the base layer 13 within the trench.
The on-voltage and the short circuit withstand capability have the trade-off relationship in the various trench IGBT""s of the constructions described above, making it difficult to satisfy both the on-voltage and the short circuit withstand capability simultaneously.
The construction of a conventional planar IGBT will now be described. FIG. 2A is a cross sectional view schematically showing the construction of the conventional IGBT of the planar gate type.
As shown in the drawing, an nxe2x88x92-type base layer 12 is formed on a p+-type collector layer 10, and a p-type base layer 13 is formed in a part of the surface region of the nxe2x88x92-type base layer 12. Also, an n+-type emitter layer 14 is formed in a part of the surface region of the p-type base layer 13. Further, a gate insulating film 16 is formed to cover the base layers 12, 13 positioned between the adjacent emitter layers 14, and a gate electrode 17 is formed on the gate insulating film 16. An emitter electrode 18 is formed on the other region. It should be noted that the emitter electrode 18 and the gate electrode 17 are electrically insulated from each other by the insulating film 19. Further, a collector electrode 20 is formed on the back surface of the collector region 10 so as to form an IGBT.
FIG. 2B is a graph relating to an impurity concentration profile along the line Y1-Y2 shown in FIG. 2A and shows the impurity concentration distribution in the active area including the channel region CH. As shown in the drawing, the profile includes the n-type impurity concentration distribution 30 in the emitter layer 14, the p-type impurity concentration distribution 31 in the p-type base layer 13, and the n-type impurity concentration distribution 32 in the nxe2x88x92-type base layer 12. The p-type impurity concentration in the p-type base layer 13 is increased to reach the highest concentration Cp0 in the position close to the junction between the emitter layer 14 and the p-type base layer 13, and the p-type impurity concentration is gradually lowered toward the nxe2x88x92-type base layer 12.
The planar IGBT differs from the trench IGBT in the gate construction. However, since the planar IGBT is equal to the trench IGBT in operation, the on-voltage and the short circuit withstand capability have the trade-off relationship in the planar IGBT, too, though the detailed description thereof is omitted.
As described above, if the on-voltage is increased in the conventional IGBT, the short circuit peak current Icp is increased, with the result that the short circuit withstand capability tsc is diminished. It follows that it is difficult to satisfy simultaneously the requirements for maintaining a low on-voltage and for improving the short circuit withstand capability.
A semiconductor element according to an aspect of the invention comprises:
a first base layer of a first conductivity type;
a second base layer of a second conductivity type formed selectively in one surface region of the first base layer;
an emitter layer or a source layer of the first conductivity type formed selectively in a surface region of the second base layer;
a gate electrode formed on that portion of the second base layer which is positioned between the emitter layer or source layer and the first base layer with a gate insulating film interposed between the gate electrode and the second base layer;
a collector layer or a drain layer formed on the other surface region of the first base layer or formed selectively on one surface region of the first base layer;
a first main electrode formed on the collector layer or on the drain layer;
a second main electrode formed on the emitter layer or source layer and on the second base layer; and
a third base layer formed in the second base layer, isolated from the emitter layer or source layer, contacting the gate insulating film; and having an impurity concentration profile along the gate insulating film, the profile having a peak closer to the first base larger than a peak of the impurity concentration profile of the second base layer.
A method of fabricating a semiconductor element according to an aspect of the present invention comprises:
selectively forming a second base layer of a second conductivity type in one surface region of a first base layer of a first conductivity type, the second base layer having an impurity concentration profile such that the point of the highest impurity concentration is positioned in a region close to the junction between the second base layer and the first base layer;
selectively forming an emitter layer or source layer of the first conductivity type in a surface region of the second base layer;
forming a gate electrode on the surface of that region of the second base layer which is positioned between the emitter layer or source layer and the first base layer with a gate insulating film interposed between the gate electrode and the second base layer;
selectively forming a collector layer or drain layer in the other surface region of the first base layer or in one surface region of the first base layer; and
forming a first main electrode in contact with the collector layer or drain layer and a second main electrode in contact with the emitter layer or source layer and the second base layer.